1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a DRAM (dynamic random access memory) that has an SRAM interface.
2. Description of the Related Art
In mobile phone communications, the amount of data handling has been on the increase because of the communication link with the Internet or the like, and the mobile phones are now required to be equipped with a large memory volume. At present, mobile phones employ SRAMs (static random access memories), which can operate with small electric current consumption. SRAMs have drawbacks in that circuit density is small, and in that an increase in memory volume results in a significant cost increase.
DRAMs, on the other hand, are suitable for constructing a large volume memory at low costs. Because of this, it is quite conceivable to use DRAMs on mobile phones in place of SRAMs. Since there is a great amount of technology accumulations in the use of SRAMs in mobile phones, however, it is preferable to provide DRAMs that act like SRAMs on the surface, rather than to redesign mobile phones to be suitable for DRAMs. Accordingly, there is an expectation that DRAMs become available that have an interface identical to that of SRAMs.
Control systems differ between DRAMs and SRAMs in many aspects. One of such differences is an address timing requirement at the time of a data read operation. In SRAMs, there are two methods of controlling read operations, one being to start a read operation by dropping a chip enable signal /CE, and the other being to start a read operation by changing an address when the chip enable signal is already at the dropped level (i.e., /CE=L).
Since there is no timing requirement in SRAMs with respect to an address at the time of a read operation, both methods described above will result in data of the last entered address being output. This will be further described below. In SRAMs, memory cells are basically flip-flops, so that nondestructive data reading is possible, i.e., the data contents will not be lost upon access to the memory cells. Accordingly, no matter how the input address changes, the output data supplied from the memory cells to an exterior of the device changes at every turn by following changes of the input address. No matter whether the data is read by dropping the chip enable signal or the address is changed when the chip enable signal is already at the dropped level, data that is being output at a given moment is the data that corresponds to the last entered address, regardless of history of address changes. If the address further changes at this moment, the output data will follow the change. In this manner, there is no timing requirement regarding timing at which an address is supplied at the time of a read operation, and an output that corresponds to a supplied address is obtained immediately in response to the supplied address given at any timing.
In DRAM memory cells, on the other hand, only destructive data reading is possible, i.e., the data contents will be lost upon access to the memory cells. In DRAMs, therefore, a restore process is necessary that restores the data of sense amplifiers in the memory cells. During the restore process, an address change to access other memory cells is prohibited. Because of this, the address supplied at the start of a read operation is stored in an internal latch, and the latched address is maintained as a fixed address during the period of data reading. It is thus impossible in DRAMs, as opposed to in the case of SRAMs, to obtain an output data at a desired timing by changing the address at the desired timing.
Because of the reasons described above, DRAMs that provide an interface compatible with that of asynchronous SRAMs generally need some timing requirements defined for their address input. For example, a drop of the chip enable signal /CE or a first change in the address signals may be detected to store an address in memory. In this case, a setup time and hold time of an access address must be defined with respect to the drop of the signal /CE or the first change of the address signals. In such a configuration, however, a wrong address will be accessed if the setup time of the address is not sufficient or if there is a long time delay from the first change of the address signals to the last change of the address signals.
Accordingly, there is a need for a DRAM that has an SRAM-type interface with no address timing requirements.
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor memory device, including a latch circuit which latches an address signal supplied from an exterior of the device, a core circuit which includes memory cells, to which access is made at the address stored in the latch circuit, and a latch timing control circuit which records a fact that the address signal is changed during an operation of the core circuit, and makes the latch circuit latch the changed address signal after a completion of the operation of the core circuit.
The latch timing control circuit described above records a fact that the address signal is changed during an operation of the core circuit, and controls an access operation to be performed on the core circuit after the completion of the operation of the core circuit.
Further, the latch timing control circuit described above makes the latch circuit latch the address signal immediately upon detecting a change of the address signal if the change of the address signal is detected while the core circuit is not operating.
Moreover, the latch timing control circuit makes the latch circuit latch the address signal immediately upon detecting a drop of a chip enable signal if the drop of the chip enable signal is detected while the core circuit is not operating.
In the present invention as described above, a read operation is performed on the DRAM core circuit at an address presented at the time of a drop of the chip enable signal, but the output data will change by following a subsequent change in the address signal. Further, if a read operation is performed first by responding to a first signal change of an address transition, a read operation is performed again with respect to a correct address as presented after the address transition when the last signal change of the address transition is completed.
This is achieved by rewriting an internal address stored in the latch circuit after the completion of a core operation rather than rewriting the internal address immediately upon detection of an address change during the core operation. In the use of a DRAM core circuit, therefore, there is no need to define timing requirements for the address signal transition time, making it possible to provide an interface that is compatible with that of SRAMs. It should be noted that when the address is changed multiple times during the core circuit operation, the output data will end up being the data responding to the last entered address.
This makes it possible to provide a semiconductor memory device that is usable in place of conventional SRAMs while the semiconductor memory device has a large memory volume and is provided at a low cost.